Vacancy expired!
- Test plan and development of the test bench and verification of high-performance SOC subsystems
- Develop and maintain methodology/flows/checks for verification team
- Work with multi-disciplinary groups to deliver verification tests and port in tests in the lab for post silicon validation
- Verification of multi-million gate ASICs with System Verilog/UVM
- Minimum of 5+ years of ASIC verification experience
- Experience or knowledge of system architecture, CPU & IP integration, power and clock domains
- Expertise in System Verilog and other high level language like C, C is a must
- Familiarity with scripting in Python or Perl
- Hands on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
Vacancy expired!