Vacancy expired!
- Own verification for various blocks in a SoC, sub-system or an IP and meet coverage goals
- Own the test-bench and enable reuse of block level UVM test-benches at sub-system and SOC level.
- Come up with a comprehensive verification strategy encompassing simulations, formal verification, HW/SW reuse and simulation performance.
- Work with cross functional IP teams for Integration verification
- Work with design team to understand Specifications and come up comprehensive test plan for quality Verification
- Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance
- SOC/Subsystem/IP DV, Debugging, problem solving
- Experience with Verilog/System Verilog, digital simulation
- Experience with Perl, Python, or similar scripting language
- Exposure to UVM is desired
- Experience with AMBA bus protocols
- Experience with C/C, assembly language
- Knowledge of low power design concepts and power management is a big plus
- Knowledge of computer architecture, cache concepts and digital design fundamentals
- Prior knowledge on ARM Coresight, Peripherals, Debug blocks, JTAG verification is an added advantage
- Strong problem-solving ability
- Strong team player and communicator.
Vacancy expired!