Vacancy expired!
- Positions are available for multiple experience levels.
- We want you to have experience in custom analog layout from floorplan, placement, routing, and verification, with extensive experience on deep sub-micron CMOS (16nm, 7nm, etc.). mmWave experience is a plus.
- Knowledge in FinFet device structures, guard-rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, and DFM etc. will be critical to your success.
- Understanding of trade-offs in matching, parasitic effects, high frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD and latch-up is key.
- Working knowledge of Cadence Virtuoso and Mentor Calibre, and proficiency in interpreting verification results of DRC, LVS, ERC, and ANT are skills you need to succeed.
- We would welcome a great teammate with excellent communication skills to work with multi-functional teams.
- Please be prepared to proactively work with circuit designers for optimal solutions to problems, and recognize failure prone circuit and layout structures.
- You can benefit from the ability to provide accurate schedule and update plans to meet project milestones.
- Knowledge of Totem, EM/IR tools, PAD/EAD and constraint editor experience would be a plus.
- Experience with Skill, Python, Perl, layout scripts for automation and improvement of flow will be helpful.
Vacancy expired!