Vacancy expired!
- MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/digital design
- Experience with Verilog and system Verilog
- Experience with VCS,
- Experience with pre-layout simulation and post-layout simulation
- Understanding of the design flow. Ability to work with the backend team
- Familiarity with AMBA APB AXI Protocol
- Familiarity with RISC/Arm or other core architectures
- Ability to create innovative architecture and solutions to customer requirements
- Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.
- FPGA design of image processing systems
- Working knowledge of SoC architecture such as CPU, GPU or accelerators
- Hands-on experience with high speed PCB design
- Hands-on experiences with silicon debug and testing
- Proficient in scripting (Perl, Python, Shell etc.)
- Familiarity with: UVM, place-and-route, STA, EM/IR/Power
Vacancy expired!