Vacancy expired!
- Perform RTL and netlist level Power analysis
- Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction
- Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
- Implement some blocks at RTL and UPF
- Ability to document and communicate clearly
- 5+ Years of experience as an ASIC Power engineer, or Physical Design engineer
- Experience with synthesis, some physical design, and power estimation tools
- Knowledge of power trade-offs in design and back end implementation
- Hands-on experience in scripting, data analysis
- BS in Electrical Engineering/Computer Science or equivalent experience
- Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)
- Python, Perl (or similar) scripting and data-post-processing tools
- Excel (or Matlab) for model fitting, data visualization and analysis
- Experience in low power design, tools and methodologies including power intent UPF specifications
- Silicon Power Characterization
- Some power profiling experience at IP/SoC level
Vacancy expired!