Verification Engineer V job vacancy

Vacancy expired!

Summary:The main function of the Verification Engineer is to work with a group of researchers and engineers to own the electrical system level verification of Facebook's products. Working closely with researchers, architects, and designers in architecting methods of electrical verification for multiple state of the art systems. Using verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs.

Job Responsibilities:• Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams• Define and track detailed test plans for the different modules and top level systems• Define, architect, design and drive implementation of scalable test infrastructure• Keep track of coverage metrics and bugs encountered and fixed• Own execution, interpretation, and reporting of electrical system level verification work status and results• Support system bring up and debug activities• Clearly communicate test plans and results

Skills:• Expertise in running Native Low Power (NLP) simulations• Working knowledge of UPF concepts and UPF simulations .• Hands on knowledge in System Verilog and UVM• Experience in verification of Full chip and SOC involving Processors .• Knowledge of definition, architecture, design, and driving implementation of test automation• Working knowledge of C , Python• Experience with firmware verification• Experience with board level verification

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Vacancy expired!

ID	#15646623
State	California
City	Menlopark
Job type	Contract
Salary	USD Depends on Experience Depends on Experience
Source	Vertisystem Inc.
Showed	2021-06-20
Date	2021-06-15
Deadline	2021-08-14
Category	Et cetera
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Job Details

Verification Engineer V

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