Vacancy expired!
- Extensive experience coding Verilog or System Verilog RTL
- Proven track record on delivering micro-architecture and RTL code that works on Silicon and meets timing for high-speed designs
- Experience interfacing with internal and 3rd party IP suppliers
- Experience scripting in Python or Perl
- Experience running Lint, CDC, and other static quality checks
- Experience with starting designs from scratch
- Familiarity with memory architecture in SoCs
- Familiarity with DDR and PCIe standards
- Familiarity with NoC or AXI Crossbars
- BS/MSEE/CE/CS with a minimum of 10 years of experience designing functional units or SOC RTL
- Experience with low power design techniques
- Proven track record of first pass silicon success
- Familiarity with C or C coding
- BS/MSEE/CE/CS with 15 or more years of experience
- Knowledge of computer architecture, especially in systolic arrays
- Experience with FPGA design and emulation
- Experience with FPGA and ASIC EDA tools
Vacancy expired!