Vacancy expired!
- Work with Architecture, RTL and Physical Design Engineers.
- Setup of industry standard Verification IP flow.
- Point of contact for verification related customer issues and deliverables.
- Development of verification testbenches and debug for EFLX IP.
- Functional and GLS verification using Verilog simulator, regressions and coverage closure.
- JTAG/DFT/ATPG verification and pattern generation.
- Development of coverage plans and metrics, drive coverage activities and test writing.
- UPF simulation and debug.
- Post-Silicon pattern generation and testing using system bench setup to validate EFLX core.
- Power/Performance benchmarking and debug.
- Must have hands-on SystemVerilog
- Must have hands-on experience with UVM/OVM.
- Must have hands-on experience in developing verification plans for SoC or ASIC architectures.
- Must have hands-on, test-writing experience with SIMD, RISCV or ARM ISA, AMBA, JTAG/DFT architectures.
- Must have hands-on functional coverage analysis and assertion implementation experience.
- BSEE/MSEE with at least 5 years of relevant industry experience.
- FPGA debug exposure.
- LPDDR4X/5, PCIe5/USB4 architecture.
- Emulation flow development in Mentor Graphics' Veloce or equivalent emulation hardware.
- Exposure to Formal Verification techniques.
- Worked with and directed external contractors.
- Development of testbench and debug for silicon validation, post-silicon bring-up and checkout; Linux-based validation using C/Python.
Vacancy expired!