Vacancy expired!
- Design verification
- UVM
- Test Bench
- Constrained-random verification
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
- Experience verifying digital logic at RTL using SystemVerilog for FPGAs and ASICs.
- Experience verifying digital systems with standard IP components/interconnects, including microprocessor cores and hierarchical memory subsystems.
- Experience creating/using verification components and environments in methodology (VMM, OVM, UVM).
- Master's degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science.
- Experience with image processing, computer vision, and/or machine learning applications.
- Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
- Experience with performance verification of ASIC components.
- Experience with verification techniques.
- Familiarity with ASIC standard interfaces and memory system architecture.
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Vacancy expired!