FPGA Verification and FPGA Design Engineer

FPGA Validation MS in Electrical Engineering, Computer Engineering or equivalent 3+ years of experience in verification, preferably in communication systems Knowledge of System Verilog, UVM principles, bash/shell scripting, MATLAB, and Git Experience with Questasim FPGA Engineer Bachelor's degree in electrical engineering, computer engineering, or other engineering discipline 2+ years of experience with Vivado or other FPGA development software 2+ years of experience in SystemVerilog, Verilog, or VHDL RTL design 2+ years of experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C, Perl, Tcl, Make, Bash Familiarity with a Continuous Integration Too Experience in designing data path and control RTL blocks