Vacancy expired!
11-Jan-2021 Requisition Number 28329BR Job Description and Requirements At Synopsys, were at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And were powering it all with the worlds most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP,interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kitsand IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. ASIC Design and Verification Intern Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products. The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips. Starting in May 2021, this 12-month internship positionwill be with our Solutions Group in Nepean on firmware and ASIC design and verification. What you will learn:
- Writing constrained-random SystemVerilog testbenches using UVM and VMM;
- Creating and analyzing functional coverage and assertion coverage, and analyzing code coverage;
- Defining and tracking verification testplans;
- Debugging RTL and gate-level simulation failures;
- SystemVerilog analog behavior modelling;
- Firmware debug
- Experience writing scripts in languages such as Perl and Unix shell.
- Familiar with Verilog and SystemVerilog.
- Familiar with ASIC design flow
- Currently enrolled in university degree program specializing in Electrical, Mathematics, Software or Computer Engineering, or similar. Must have previously completed BS and be pursuing MS degree or higher.
Vacancy expired!