Silicon DV Engineer V job vacancy in Remote, California Digital Intelligence Systems, LLC

Vacancy expired!

Wish List/ Nice to Have:

Experience in GPU, Display, or Imaging Pipeline Silicon development.

Experience in development System Verilog UVM testbench environment from scratch

Experience with Software/Hardware Co-simulation (DPI/VPI)

Experience with C/C modeling of the Hardware Systems

Experience with verification of high speed interfaces like MIPI

Experience with on-chip bus protocols (AXI, AXI-Lite, AHB, OCP)

Experience with post-silicon lab/bench test/validation

Experience with UPF based simulation flow

Education

Bachelor's degree in electrical/Computer Engineering or Computer Science

Must have skills

What are the top non-negotiable skill sets required for this role?

DV (system Verilog, C/C)
Strong DV background (test plan development, test writing, UVM)

Duties:

Develop and implement test/verification plans, methodologies and tool flows for graphics/display IPs

Define and implement IP/SubSystem verification plans, test benches and simulation/emulation coverage leading to fully functional IPs/SubSystems/SoCs

Define and implement system/integration tests

Work with cross functional teams to identify best verification methodology

Support integration of IP block tests into larger SubSystem or SoC environment tests

Implement testbench and scoreboards / checkers.

Implement test sequences as per plan and debug failures

Achieve 100% functional, code coverage

Digital Intelligence Systems, LLC (DISYS) is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.

Vacancy expired!

ID	#46216269
State	California
City	Remote
Job type	Contract
Salary	USD $85.00 - $90 per hour 85.00 - 90 per hour
Source	Digital Intelligence Systems, LLC
Showed	2022-10-04
Date	2022-10-02
Deadline	2022-11-30
Category	Et cetera
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Job Details

Silicon DV Engineer V

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