Vacancy expired!
Sr. ASIC verification Engineer Permanent Position San Diego, CA s Responsibilities: As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis. You will be responsible for building functional verification infrastructure, understanding the expected design functionality, developing test-plans as well as guiding the functional verification of complex SoCs by deploying UVM until coverage goals are achieved in order to insure the continued commercial success of our high quality products.
Required Skills/Experience: 4-8 yrs. of ASIC Verification experience 3+ yrs. of working experience in UVM Experience with scripting languages. Good amount of experience on Digital Logic design techniques and principles, SoC architecture, including ARM CPUs, communications peripherals, multi-domain clocking, power management, AMBA bus protocols such as AHB and AXI. Experience on testbench automation, industry standard bug tracking, and regression mechanisms, code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions, and architectural performance testing to achieve coverage. Strong in problem solving Strong team player and communicator Education: Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering and/or Electronics & Satellites Eng Comments for Suppliers: 01/12 - New request; supplier call details to be sent via email. Position will be working remotely until the WFH policy is lifted. Seeking candidates who are local or willing to sit onsite after WFH policy is lifted.Vacancy expired!