Vacancy expired!
- Lead the design and implementation of verification methodologies, test plans, testbenches, infrastructure, and platforms
- Work with ASIC designers and architects to produce thoroughly verified, robust IP
- Represent verification methodologies in front of key customers and executive management
- Architect IP development and productization, quality assurance, and release automation flows
- BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute
- 12+ years of experience working as a verification engineer or related field
- Strong written and verbal communication skills:
- Ability to explain complex concepts in front of both a technical audience and customers/management
- Strong desire to take ownership of all verification aspects of a project, including team and methodology leadership
- High technical competence that includes a track record of on-time, effective verification of complex digital designs
- Solid understanding of standard ASIC verification techniques, including:
- Test planning
- Testbench creation
- Code and Functional coverage
- Directed and random stimulus generation
- Assertions
- Solid understanding of verification methodologies, especially UVM (SystemVerilog)
- Comfortable in a Unix development environment
- Familiarity with advanced verification techniques (fault/stimulus injection, FPGA prototyping)
Vacancy expired!