Job Details

ID #41109965
State California
City Sanjose
Job type Contract
Salary USD $70 - $90 70 - 90
Source Xoriant Corporation
Showed 2022-05-18
Date 2022-05-16
Deadline 2022-07-15
Category Et cetera
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Design Verification Engineer

California, Sanjose, 95101 Sanjose USA

Vacancy expired!

Job Title: Design Verification Engineer

Location: San Jose, CA

Duration: 6+ months

(5+ years of experience is mandatory)

We can do w2 or c2c

Responsibilities:
  • Triage regression failures and make testbench updates
  • Debug functional errors in RTL model using simulation and debug tools
  • Maintain efficient and clean regression status
  • Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification
  • Review Architecture and Micro-Architecture specifications
  • Closely work with Architects and RTL designers
  • Define, maintain and execute unit level and/or Cluster level verification testplans
  • Generate and run Testcases on logic simulation models
  • Code Functional coverage models and System Verilog assertions
  • Drive Functional Coverage and Code coverage to closure

Requirements
  • 5 + year s industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, OOP/C
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench
  • Excellent working knowledge of scripting languages such as Python or Perl
Thanks & Regards,Lekha DholeDesk : /

Vacancy expired!

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