Vacancy expired!
- Hands-on responsibility from synthesis to place and route of a GPU block through signoff flows including timing and physical verification
- Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment
- Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable
- Interact with RTL counterpart to resolve design issues pertaining to block closure
- Optimize GPU block to meet aggressive power/performance/area targets
- BSEE, Computer Engineer or comparable and 3 + years of experience
- Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with some experience in taping out designs
- Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools
- Experience in block level floor-planning, implementing power grid and power/area/performance optimization
- Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python · Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
- Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must
- Preferred candidate will possess the following:
- Experience with 16nm Finfet or smaller process nodes
- Experience with design implementation of GPU blocks and standard industry standard tools is advantageous
- Ability to read Verilog is preferred · Hands-on experience with clock tree synthesis (CTS)
- Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage
Vacancy expired!