Vacancy expired!
Verification Engineer for Hardware & Chip R&D (System Verilog)
Summary: The Network Switch Group has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group develops ASIC's for L2/L3 switch routing. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 400Gb/s speeds as well as various line interfaces and protocols. Responsibilities:- Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips
- Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems.
- Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains
- Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment as well as leveraging high performance verification platforms such as testbench acceleration and Incircuit emulation as required.
- Executing the verification process to completion presilicon using various functional and code coverage metrics as measures of completion
- BSEE or equivalent, with concentration in digital design and excellent academic standing. Total engineering minimum experience required is typically a BS degree and 8+ years of experience, or a PhD and 3+ years of experience or equivalent.
- Hardware description languages (Verilog/SystemVerilog/SystemC/UVM),
- High level languages (C), scripting languages (Perl, Tcl) and Object Oriented Programming (OOP).
- Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog, SystemC, C/C, Perl, TCL/TK
- Strong understand and prior experience of endtoend verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production
- Excellent verbal and written communication skills.
- Masters in digital design with 5+ years of experience
- Experience in Universal Verification Methodology (UVM)
- Ability to build a bench from scratch
- Latency performance testing
- Experience with Traffic Management Verification
Vacancy expired!