Vacancy expired!
- Create UVM testbench Environment, interfacing with Digital AMS and Software
- Develop infrastructure, testbenches, tests, and coverage to ensure proper functionality
- Collaborate with ASIC and software design teams to develop testplans
- Design, develop, and maintain modular and reusable UVM testbenches for Celestial ML custom blocks.
- Confirm test completeness through code and functional coverage
- Provide technical leadership and mentoring
- Requires 5+ years of experience with UVM Testbench Infrastructure
- In depth knowledge of UVM testbenches, stimulus, constraints, and testing
- Extensive experience with System Verilog, Python, and some experience with C
- Experienced with random testbench implementation, code and functional coverage
- Experience with PCIE, AXI-4, ARM standards beneficial
- Experience with formal verification preferred.
- Prefer extensive knowledge of Python test infrastructure integrating Jenkins, git, JIRA
- Some knowledge of ML, AI trends, and HW accelerator landscape, preferred.
Vacancy expired!