ASIC Verification Engineer - Verilog, C, VCS @ Santa Clara, CA

Job Title: ASIC Verification Engineer Location: Santa Clara, CA Duration: 9+ Months USC Please note: This will be a remote role for now but will be expected to move onsite as soon as restrictions are lifted. Preferred candidates will be local to the San Jose, Santa Clara areas. Must be able to work West coast hours. Minimum Skill Requirement: Primary task is to port simulation models that work in VCS to three other simulators, and test mixed-language (VHDL) simulation for all four simulators. Secondary tasks will involve debugging failing simulations Must be able to perform Simulation using VCS, Questa, Xcelium and Riviera and be able to understand and debug simulation testbenches. Familiarity with Spyglass and CDC Background in UVM and Design Validation is preferred We are Iooking for an individual to fill a position for a Iogic - Verification engineer. Candidates must have experience performing ASIC - Verification based on architectural/micro-architectural specification review and analysis followed with definition of - Verification requirements. The person in this position will also have the following responsibilities: Educational requirements for this position are a BSEE/CE minimum, MS preferred. Also required is 7-9 years. experience in ASIC Iogic - Verification and strong software skills with experience using 1 or more of the following Ianguages: System - Verilog/Verilog, Perl, C/C. Candidates should also have experience with RTL simulators, - VCS preferred, experience specifying and developing test bench components, specifying, developing, and debugging functional tests, and experience specifying, implementing and analyzing functional coverage.