Design Engineer-Verilog/AI/Data Cache

California, Santaclara Santaclara USA
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Job Description

Role: Design Engineer-Verilog/AI/Data CacheLocation: Santa Clara, CAEmp Type: Full Time JobInterview: Phone/Skype

What you'll doing:Working on state of the art data cache architecture serving high performance AI processing elements.

Skills needed:We are looking for 2 to 4 years of experience in the following areas (will consider bright candidates with lower experience)A) Understanding of cache pipeline design and microarchitectureB) Logic design experience with state of the art deep submicron technologies specifically low power design techniquesC) Strong understanding of processor and computer architectureD) Verilog / system Verilog / Synthesis / STA (Stating timing analysis) / CDC / LINTE) Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus

Additional Information

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Job Details

ID #3630785
State California
City Santaclara
Job type Full-time
Source Synaptein Solutions
Showed 2020-03-25
Date 2020-03-23
Deadline 2020-05-22
Category Et cetera
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