Vacancy expired!
- 5+ years of Rich FPGA design experience.
- 5+ years of RTL Development using Verilog, System Verilog, VHDL
- Mipi, camera or video experience
- Xilinx experience
- Demonstrated experience working on FPGA Design projects, including work with SOC (ARM/RISC-V CPU based), MIPI, XAUI, USB, Flash, SDIO, PCI-E, and DDR# Interfaces.
- Familiarity with Synopsys (HAPS, Proto-compiler) and Xilinx tools/IPs for FPGA Design and implementation.
- Strong coding, debugging skills on both UVM and FPGA Platforms
- Hands on experience with Debuggers like Lauterbach, J-Link, ARM-DS, Testers & Scope.
- Proven expertise in one or more of the following domains: CoreSight, SoC-400, SoC-600, OCP, AXI, ACE, AHB and APB
- Familiarity with revision control concepts and tools (e.g. Subversion)
- Experience with Perl, Tcl, Python, Unix scripting.
- HAPS/ASIC/SOC experience is highly desired
- Completing implementation in RTL, RTL/netlist verification and evaluating Xilinx Vivado synthesis and P&R results for performance and cost
- Ensuring robust and complete timing constraints and evaluating STA results.
- Balancing performance, area, power, complexity and timing
- Determining and executing development, integration, bring-up and test plans.
- Working closely with firmware and verification teams during specification, development, Integration and Verification phases and deliver working FPGA platforms
- Interfacing to third-party IP
- Client interface
Vacancy expired!