Vacancy expired!
- Completing implementation in RTL, RTL/netlist verification and evaluating Xilinx Vivado synthesis and P&R results for performance and cost
- Balancing performance, area, power, complexity and timing
- Working closely with firmware and verification teams during specification, development, Integration and Verification phases and deliver working FPGA platforms
- Experience with RTL Development using Verilog, System Verilog, VHDL
- Experience working on FPGA Design projects, including work with SOC (ARM/RISC-V CPU based), MIPI, XAUI, USB, Flash, SDIO, PCI-E, and DDR# Interfaces.
- Familiarity with Synopsys (HAPS, Proto-Compiler) OR Xilinx tools/IPs for FPGA Design and implementation.
- Coding, debugging skills on both UVM and FPGA Platforms
Vacancy expired!