Senior Verification Engineer

We are looking for

• Participate in the functional verification of IP cores for a modern SOC development effort.
• Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
• Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
• Be familiar with hardware modeling and assertion-based verification methods.

• Minimum 5 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
• Strong background in C/C development in a Linux Environment.
• Strong debug skills and experience with debug tools.
• Proficient in Object Oriented programming.
• STL, computer architecture and data structures.
• Knowledge, Perl and Makefiles.
• Experience in Verilog/SystemVerilog,

• Experience in the C/Verilog environment is a plus.
• Design coverage experience is a strong plus.
• Strong analytical skills and attention to detail.
• Excellent written and communication skills.

• Microsoft Windows.
• Unix.

• C.
• C

• Perl.