Vacancy expired!
Position:VerificationEngineerLocation:Santa Clara CA (Initially this position would start asREMOTE/ Telecommutework due to COVID situation but eventually when the COVID restrictions willbe lifted, this would goONSITEin Santa Clara CA)Format: Full TimeDescription:
- Develop test benches in UVM, SystemVerilog, Verilog, C, C and other languages.
- Write test plans for digital signal processing logic blocks, control logic blocks, general-purpose processor cores and other digital logic devices.
- Write and debug tests for a complex media processor in UVM, SystemVerilog, Verilog, C, C, Perl, Python and other languages.
- Developverificationtools.
- Perform coverage analysis using CAD tools.
- Perform system-levelverificationof Ambarella's Video Input block as well as other blocks.
- Perform BlockVerificationof Ambarella's very complex CABAC compression block.
- You must possess a MSEE/CE degree.
- Knowledge of video compression and decompression algorithms.
- Knowledge of different types of memories and memory subsystems; e.g., DDR4, LPDDR3, LPDDR4.
Vacancy expired!