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Intro: Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities - we're just getting started.Summary: Facebook is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications.Required Skills: Define the power specification at system and module level for Idle, TDP, Typical use cases.
Develop power modeling infrastructure in Python/C.
Work with or develop architectural simulators in order to model performance and power.
Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout.
Optimize design for low-power with the understanding of system level concepts.
Evaluation and Implementation of low-power design techniques at different levels of abstraction.
Power characterization on silicon: idle, TDP, use case power & debug power issues on silicon.
Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors to select and deploy the appropriate power estimation tools.
Collaborate with internal HW/SW Co-design, Architecture, Design, DV, and Emulation teams for power flows, optimization and estimation.
Minimum Qualifications: B.S. or M.S. degree in Computer Engineering, Computer Science or Electrical Engineering
Understanding of ASIC design process and knowledge of leakage and dynamic power, and impact of environment and manufacturing process on power
Experience with modeling and design with C/Python or an equivalent high level language
Knowledge of front-end and back-end ASIC tools
Experience with RTL design using SystemVerilog or other HDL
Experience managing multiple design releases and working with cross functional teams to support and debug power issues
Experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments
Experience with communicating across functional internal teams and with vendors
Preferred Qualifications: Experience with architectural performance and power models at SoC and system level
Low-power design techniques such as clock-gating, power-gating, DVFS, AVS
Experience architecting systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of tradeoffs between performance and power
Post-silicon bringup, debug and identify issues on emulator and RTL
Industry: InternetEqual Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
Vacancy expired!