Vacancy expired!
At eXcell, we set you up for job success right from the start. Our precision recruiting process aligns the right fit for the right people. Our client has a new opportunity for an on-site Verification Engineer in Fort Collins. Scope of Activity:
- IP verification in UVM
- Position corresponds to pre-silicon verification for IP level verification
- Coverage and assertion development with coverage closure
- Meeting with other team members to determine functionality protocols
- Designing and reviewing verification methodology based on plans / designs and failure points
- Determining testing environments and verification tools
- Instituting and tweaking testing mechanisms and protocols
- Conducting quality control inspections
- Writing up final test procedures
- Able to work in a dynamic and fast paced environment where both time to market and quality are extremely important
- UVM and SystemVerilog experience required
- Experienced Design Verification Engineer for IP level functional verification
- Experienced in SystemVerilog
- Expertise in UVM methodology / verification techniques
- Knowledge of UVM for creating: testbench infrastructure, agents, testcases, sequences, and scoreboards
- GIT revision control experience and APB protocol knowledge is a big plus
- Detailed knowledge of testing methodology
- Knowledge of industrial manufacturing procedures
- Excellent analytical and troubleshooting skills, with a keen eye for detail
- Advanced verbal and written communication skills
Vacancy expired!