Vacancy expired!
Title: Design Verification Engineer
Mandatory skills: Silicon Design,Design Verification, Geometry Subsystem, GFXIP,test planning, test writing, Cmodel debug,Linux, scripting, C/C, System Verilog, UVM Verification Methodology,Object Oriented Programming Description: The position is for Design Verification Engineer for Geometry Subsystem Team (part of GFXIP). The responsibilities include (but not limited to) working with designers/architects on test planning, test writing, regression debug. Writing functional coverage, assertions, checks, support Cmodel debug etc.Skillsets: Linux, scripting, C/C, System Verilog, UVM Verification Methodology, knowledge on verification methodology/Flow and Object Oriented Programming concepts. (optional skillset: formal verification)Education: Bachelor's DegreeNote :Preferably onsite, remote an option VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions. Contact Details : VIVA USA INC.3601 Algonquin Road, Suite 425Rolling Meadows, IL 60008 | http://www.viva-it.comVacancy expired!