Vacancy expired!
Title: Verification Engineer - Senior
Mandatory skills:C, C,ASIC development, embedded programming, hardware architecture,Cadence NCSIM, Synopsys VCS,UVM, OVM,Verilog, System Verilog, OOO coding techniques,Ruby, Python, Tcl, BASH,UNIX, Linux,custom verification tools, test methodologies, debug tools, design verification, test plan Description: The candidate would participate on a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system. The candidate would be responsible for carefully documenting and executing test plans consisting of directed and random tests to be run under simulation and hardware acceleration. Experience with hardware modeling, assertions, and formal verification methods are valuable assets. The candidate would be expected to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within aggressive, market-driven schedules.Education and Experience Required:Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.5+ year(s) of proven verification experience on large ASIC development projects or equivalent embedded programming experience with a deep understanding of hardware architectureVery strong background in C/C/OOO coding techniquesExperience with Verilog and/or System VerilogExperience working with Cadence NCSIM, Synopsys VCS or equivalentExperience working with UVM, OVM or equivalentExperience with scripting languages, Ruby/Python/Tcl/BASH/etc.Working knowledge of UNIX/Linux operating systems and debug toolsInterest in developing custom verification tools and driving new test methodologiesStrong analytical skills and attention to detailExcellent written and communication skillsTeam player with proven leadership skillsResponsibilities:Understand the architecture of the Display IP and functional block being designedBuild SystemVerilog and/or C/C models and test sequence libraires for simulationBuild test bench and monitors for DUTCompose test and coverage plan, and validation vectors to ensure functional completenessDebug function/performance bugs of Display IP VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions. Contact Details:Please send your resumes and one of our recruiter will get in touch with you. VIVA USA INC.3601 Algonquin Road, Suite 425Rolling Meadows, IL 60008http://www.viva-it.comVacancy expired!