Vacancy expired!
- Bachelor's Degree and 6 to 10 years work experience (or equivalent experience)
- Experience planning, architecting, developing, and using constrained random, self-checking test benches in SystemVerilog 8 plus years/UVM, OVM, and/or VHDL
- Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence)
- Proven track record of managing and executing schedules, and driving tasks to closure. Candidates should also be comfortable multitasking because they may be asked to support multiple projects.
- Strong communication and documentation skills
- Experience developing and implementing test plans.
- Ability to work effectively in a multi-site or borderless environment
- Perl/Python
- C/Java
- Git/Jira/BitBucket
- Digital Signal Processing
- Matlab/Simulink
- Working knowledge of VHDL
- FPGA Design Experience
- Experience creating reusable Verification IP.
- Experience leading small to medium teams with accountability for cost, schedule, and quality
- Experience driving process.
- Demonstrated mentoring skills
Vacancy expired!