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Job Title: RTL Design Engineer Job Location: Hillsboro, Oregon (Remote) Duration: 6+ months Remote with ability to work US Pacific time business hours "We are seeking experienced RTL design engineer contractors to implement IP for digital blocks, including ARM blocks such as A53 or A55 on leading-edge testchip vehicles. Minimum experience with proficiency in defining block level specifications and performing RTL coding for SOC blocks, working with the Physical Design team to optimize physical constraints and timing, and must be well-versed in Pre Silicon verification and debug strategies. 5+ years of experience with code quality tools such as Spyglass, LINT, CDC, experience with System Verilog and Perl/TCL/Python. Familiarity with Intel's design environment and methodologies such as CTH2 is highly desirable. Experience: at least 5 years of experience, Master's degree or BS degree with more work exp in Lieu of master's degree.
Vacancy expired!