Silicon Power Architect

Facebook AR/VR focuses on delivering Facebook's vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.Facebook AR/VR is looking for a Silicon Power Architect who will work with a world-class group of researchers and engineers. This ideal candidate will understand the full spectrum of silicon power modeling, analysis, optimization and projections from algorithms on generic compute units to custom silicon IP blocks, traditional compute benchmarking, and SOC and System level implications. The candidate will work with architecture, design, backend, system and verification teams and drive the team towards implementing the most power efficient design.

• Define power architecture that includes functions such as image compute, CPU/GPU benchmarking, throughput and QoS analysis, power management architectures and detailed modeling and analysis.
• Surpass state of the art for metrics such as compute, bandwidth and power consumption.
• Work across disciplines, brainstorm big ideas, build new methodologies, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product.
• Understand the tradeoffs between general purpose and custom compute mechanisms, be able to model data-flows, and create detailed cost/benefit analysis.
• Guiding a small team of other architects and designers in undertaking power analysis, modeling, and projections. They will produce models matching the proposed ASIC implementation, and produce detailed tradeoff analyses for executive review and product roadmap decisions.
• Work on running power simulation and analyzing results and guiding design team in power optimization.
• Work on post silicon model to hardware correlation.

• 7+ years of experience with production silicon including at least one product shipped.
• Experience with methods for partitioning a solution across hardware and software, digital, and other multi-disciplinary boundaries in a system solution.
• Experience evaluating architectural trade-offs of performance, power, and area.
• Experience employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary system issues.
• MSEE or equivalent experience.
• Knowledge of low power design principles across RTL, design and system level.

• Experience in top down high-level-model to HW power modeling of system use cases.
• Experience in technology node scaling and projections.
• Experience in custom IP block power estimates.
• Experience programming in C or Python.
• Experience working effectively as an individual and in a multidisciplinary team.
• Capable of dealing with ambiguity with a fast changing consumer electronics field.
• Results oriented, self-motivated, proactive with demonstrated creative & critical thinking.
• Ability to collaborate and/or lead in a team environment.