Job Details

ID #49560516
State Texas
City Austin
Job type Contract
Salary USD $70 - $80 70 - 80
Source Pyramid Consulting, Inc.
Showed 2023-03-27
Date 2023-03-24
Deadline 2023-05-23
Category Et cetera
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Design Verification Engineer

Texas, Austin, 73344 Austin USA

Vacancy expired!

Our client is in immediate need for a talented

“Design Verification Engineer”; with experience in the

IT Industry. This is a

12 Months contract opportunity with possible extension (also open for

Full Time – Permanent role) and is located in

“Bay Area, CA / Austin, TX”. Please review the job description below and contact me ASAP if you are interested.

This requirement is open for both Remote as well as Onsite work

Par Rate Range: $70/hr to $80/hr

Salary Range: $170K to 185K PA (7-10% Bonus Included) Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).

Job Role:
  • As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
  • If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
  • You will develop testbench components and stimulus using SystemVerilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.

Job Requirement:
  • Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
  • Understanding of verification tools like Simulator, Synthesis etc.
  • Hands on experience on C/C, System Verilog, UVM, SystemC, RTL
  • Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
  • Excellent written and verbal interpersonal skills
  • Self-motivated and great teammate

Qualification:
  • Typically requires minimum of 2-10 years of experience in System Verilog, UVM.
  • BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering.
  • ME/M.Tech in VLSI or Microelectronics is a plus
Our client is a leading

IT organization and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration. Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Vacancy expired!

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