Vacancy expired!
Job Title: Design Verification Engineer Location: Austin, TX or Redmond, WA Contract: 12+ Months Description:
- Hands on Verification environment development experience using Verilog and SV
- Development of verification plans
- Verification experience with various ARM AMBA protocols (AXI, AHB, APB)
- SoC Verification experience that include complex IPs (example: ARM core, PCIe, USB, DMA controller, DDR, etc)
- Development of test cases and ensuring coverage and performance goals are achieved for IP and SOC level
- Good knowledge and hands on experience with SV/ UVM based verification environment
- Good knowledge and hands on experience with UPF/ power aware verification
- Experience in C based verification
- Experience in GLS
- Experience using Perl and Python scripts is a plus
- Tools experience: VCS, Simvision, Verdi
Vacancy expired!