Vacancy expired!
- Note: Secret required, TS preferred. Must be willing to be on site as needed. There may be some limited opportunity for WFH. No opportunity for 100% remote work.
- We are seeking a talented senior engineer to join the digital design team. The successful candidate will contribute to FPGA development including design, synthesis, verification, validation, test & support.
- Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital FPGA efforts.
- Applicant should also be familiar with embedded software development for FPGA SoCs.
- Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware.
- Direct experience with embedded FPGA design is required.
- BSEE with 6 years relevant experience
- Fluent in Verilog/System Verilog Coding
- Understanding of networking (specifically Ethernet/IP) layered models and protocols
- Implementation of FPGA functions to accelerate SW (checksum engines, packet parsing, etc.)
- Ability to debug designs simulated in a UVM environment
- Capability to learn Libero tools, PolarFire (SoC) devices, and IP
- Capability to learn layered communications protocols
- Experience with joint design/debug with embedded software
- Experience debugging FPGA fabric designs with embedded processor software on HW
- Capability for evaluating trade space for adding new features to FPGA fabric and/or software (knows strengths of each technology and can optimize based on requirements)
- Experience with design closure including timing, power and area for SWaP constrained designs
- Familiarity with high speed interfaces (10Gbit Ethernet, PCIe, DDR4, LVDS, etc)
- Experience with Linux and scripting languages
- Communicate effectively with SW engineers (in support of program execution)
- Strong analysis and problem solving skills
- MSEE with 6 years relevant experience
- Experience with 10Gbit Ethernet and IP in HDL designs
- Understanding of higher layer protocols (TCP, UDP, etc.)
- UVM skills (Test and/or Test Bench development)
- Microchip Libero/PolarFire development
- Experience with Microchip (Microsemi/Actel) IP
- Experience with embedded processors within FPGAs
- Experience with Xilinx Vivado design tools and Petalinux
- Experience with Matlab/Simulink
- Experience working with PCB designers
- Secret required, TS preferred.
Vacancy expired!