Senior Signal Integrity Engineer (NetSec)

Your CareerAs a contributor in the Network Security Platform Hardware development team, you will play a key role in the complete design cycle of Palo Alto Networks Firewall and SD-WAN hardware including:  selecting components; modeling and simulating memory and serdes interfaces; modeling PDN networks; defining PCB routing constraints; reviewing PCB layout; developing test plans; performing hands-on measurements to validate critical interfaces.  Within the Hardware team, you collaborate closely with Board Design, ASIC Design, PCB Layout, and Validation Test.  You will also collaborate cross-functionally with Product Management, Platform Software, and Operations Supply Base Management & Component Engineers.Your ImpactCollaborate with a cross-functional team including:  ASIC, Board design, PCB layout, Operations supply base management, Platform SoftwareEvaluate design tradeoffs and optimize design performance / risk / cost / manufacturabilityContribute to ASIC package design for SIModel complex 3-dimensional structures in field simulation softwareSimulate Channel Analysis for high speed serdes and memory interfacesDesign and analyze high-speed serial links (56G and beyond) and their compliance to internal specs and standards Create and verify module/package and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi-chip-module designsModel and analyze power delivery networks for ASIC/package/module and PCBCreate SI test plan for coverage of all serdes, memory, and external IO interfacesDrive creation and implementation for required test infrastructure (tools, scripts, etc.) with external vendors and internal software teams Perform lab measurements for design validation and simulation correlationsDrive methodology enhancements and automation - improving performance and efficiencyMentor junior engineers and interns